1. Field of the Invention
The present invention relates to the design and manufacturing of semiconductor chips. More specifically, the present invention relates to a method and an apparatus for computing feature density of a chip layout.
2. Related Art
The dramatic miniaturization of integrated circuits has been a key driving force behind recent technological innovations. This miniaturization has largely occurred due to rapid advances in various fabrication technologies. However, these rapid advances have been accompanied by increasingly stringent constraints (design rules) that limit the amount of allowable process variation during manufacturing.
One such design rule involves ensuring that the feature density is within a range of permissible values. Feature densities outside this range can result in peaks and valleys on the wafer's surface, which can adversely affect chip manufacturability and yield. Hence, it is very important to identify areas within a layout that violate a feature density design rule.
Present techniques for computing the feature density of a layout move a window across the layout in discrete steps, and calculate the feature density within the window at each step. This allows the technique to generate a database of window locations and their associated feature density values, which can then be used to identify areas within the layout that violate the feature density design rule.
Unfortunately, present feature density computation techniques have an inherent tradeoff between accuracy and computational time. Specifically, decreasing the step size increases the accuracy, but it also increases the computational time. On the other hand, increasing the step size reduces the computational time, but it also decreases the accuracy of detecting design rule violations.
Hence, what is needed is a method and an apparatus for computing feature density of a layout without the above-described problems.